Monochrome LCD
I salvaged this screen from a dead copier. It has a CCFL backlight with a seperate inverter and a 10-pin connector. It has two possible part numbers printed on it: CCL-E145V and 56AAA1357B. I could not find any information on the display itself, but I found the datasheets on the chips and from that figured out the required timing. The display has one M5839B and three M5260 driver chips. The screen's resolution is 192x64.
Front of LCD
Back of LCD
Pinout
Pin 1 is labelled on the back of the board. It is the pin near the center of the board.
| Pin | Description |
|---|---|
| 1 | Vcc (+5V)(connected to pin 10) |
| 2 | GND (connected to pin 9) |
| 3 | /POFF (1 = LCD bias enabled) |
| 4 | Not connected (could be connected to DF) |
| 5 | RDI (row data input) |
| 6 | RCP (row clock pulse), column LOAD, 4017 /CP1 |
| 7 | CCP (column clock pulse) |
| 8 | CDI (column data input) |
| 9 | GND (connected to pin 2) |
| 10 | Vcc (connected to pin 1) |
All signals are inputs.
Electrical notes
Drive /POFF high to turn on the display.
A 4017 and 7474 on the board are used to change the polarity of the voltage applied to the LCD elements periodically so that the average voltage is zero.
An SCI7661M is used to generate the negative supply (about -10V). Two of the three capacitors it used were bad, resulting in a negative supply voltage of about -6V. This prevented the LCD elements from being driven hard enough to show a pattern when a correct waveform was given to the drivers. This confused me for a while because without a description of the correct timings I couldn't tell if I was driving the screen correctly, and nothing showed up unless multiple rows were driven at the same time (with the same data, so the display was blurred). The replacement caps are visible on the back of the LCD.
Row driver LOAD is tied high.
4017 drives 7474 which drives DF.
Drivers shift on the falling edge of CCP and RCP.
Max clock frequency is 3.3MHz.
Pulse RCP at the end of each line.
RCP must not be high during falling edge of CCP.
RDI must be high during falling edge of RCP at the end of the first line.
Connection
I removed the connector on the LCD screen and soldered color-coded wires to the pads. I only used one of each power supply pad. I crimped a pin header socket contact to each wire and insulted it with heat-shrink tubing. I didn't make a nice connector like I did for the color LCD above because there aren't that many wires and I ran out of header housings anyway.
This screen requires 5V which is supplied by a 7805 on the breadboard. The 7805 is powered by unregulated power from the adapter powering the D2FT board.
Code
The code is organized the same way as for the color LCD above. LCD_Sync generates the dot clock for the LCD because RCP must change on a different clock edge from CCP.
The LCD with the test code running.
The VHDL code can be downloaded here.